1. Field of the Invention
Exemplary embodiments of the present invention relates to a technology for fabricating a semiconductor device; and, more particularly, to a high-voltage semiconductor device.
2. Description of Related Art
A high-voltage semiconductor device is formed of the combination of extended drain MOS (EDMOS) transistors and laterally doable diffused MOS (LDMOS) transistors. Since each of the EDMOS transistor and the LDMOS transistor has high input impedance than a bipolar transistor, power gains of the EDMOS transistor and the LDMOS transistor are large, and a gate driving circuit may be simply implemented. Also, because each of the EDMOS transistor and the LDMOS transistor is a unipolar device, delay does not occur, where the delay occurs due to accumulation or recombination of minority carriers during a long turn-off.
FIG. 1 is a cross-sectional view of a conventional laterally double diffused MOS (LDMOS) transistor; and FIG. 2 is a cross-sectional view of a conventional extended drain MOS (EDMOS) transistor. In the drawings, the LDMOS transistors and EDMOS transistors each having an N channel is illustrated. Also, FIG. 1 shows two LDMOS transistors disposed symmetrically based on a pickup region.
Referring to FIG. 1, the conventional LDMOS transistor includes a N-type well 12 formed in a substrate 11 having a device isolation layer 21, a P-type body region 13 formed over the N-type well 12, a gate electrode 20, a gate insulation layer 19, an N-type source region 16, an N-type drain region 15, an N-type impurity region 14, and a P-type pickup region 17.
The gate electrode 20 is formed over the substrate 11 to be partially overlapped with the P-type body region 13. The gate insulation layer 19 is interposed between the gate electrode 20 and the substrate 11.
The N-type source region 16 is formed in the P-type body region to be arrayed at one end of one side of the gate electrode 20. The N-type drain region 15 is formed over the N-type well 12 to be spaced apart from one end of another side of the gate electrode 20. The N-type impurity region 14 is formed in the N-type well 12 to surround the N-type drain region 15. The P-type pickup region 17 is formed in the P-type body region 13.
Since the length of a channel region C1 of the LDMOS transistor is short, the LDMOS transistor is used as a switching device controlling a large amount of current in the high-voltage semiconductor device. In order to form the channel region C1 having a short channel length, the channel region C1 is formed by selecting impurities having different diffusion characteristic and applying a double diffusion method. The channel region C1 of the LDMOS transistor is defied by overlap region of the body region 13 and the gate electrode 20.
Since the LDMOS transistor uses the double diffusion method to form a short channel region C1, the length of the channel region C1 cannot be varied. Thus, the LDMOS transistor may not be used as an analog device to control the operation of the high-voltage semiconductor device. Herein, the analog device is a device having a saturation region that a magnitude of a drain current ID is maintained as fixed value even though a magnitude of a voltage VDS increases, where the voltage VDS is a voltage between the N-type drain region 15 and the N-type source region 16.
Accordingly, in order to provide the analog device controlling the operation of the high-voltage semiconductor device, a conventional extended drain MOS (EDMOS) transistor shown in FIG. 2 is introduced.
Referring to FIG. 2, the conventional EDMOS transistor includes a P-type first well 22 and an N-type second well 23 formed over a substrate 11 having a device isolated layer 21, a gate electrode 20, a gate insulation layer 19, an N-type source region 16, an N-type drain region 15, an N-type impurity region 16, a P-type pickup region 17, and a P-type impurity region 24.
The P-type first well 22 and the N-type second well 23 are functioned. The gate electrode 20 may extend over both a portion of the P-type first well 22 and a portion of the N-type second well 23. The gate insulation layer 19 is interposed between the gate electrode 20 and the substrate 11. The N-type source region 16 is formed in the P-type first well 22 at one side of the gate electrode 20. The N-type drain region 15 is formed in the N-type second well 23 at another side of the gate electrode 20. The N-type impurity region 14 is formed in the N-type second well 23 to surround the N-type drain region 15. The P-type pickup region 17 is formed in the P-type first well 22. The P-type type impurity region 24 is formed in the P-type first well 22 to surround the P-type pickup region 17.
Herein, a channel region C2 of the EDMOS transistor may be defined as a surface area of the substrate 11 where the gate electrode 20 is overlapped with the P-type first well 22. The length of the channel region C2 of the EDMOS transistor is longer than the length of the channel region C1 of the LDMOS transistor. It is easy to vary the length of the channel region C2 by adjusting a line width (area) overlapping the P-type first well 22 and a gate electrode 20. Thus, the EDMOS transistor is used as the analog device in the high-voltage semiconductor device.
When one type transistors of the LDMOS transistor or the EDMOS transistor are used, it is difficult to achieve desired operating characteristics. That is, the conventional high-voltage semiconductor device has to be formed of the combination of the LDMOS transistor and the EDMOS transistor. Thus, structures of the high-voltage semiconductor device are complex, and the implementation is not easy. Also, high level of the fabrication process is required due to the structure complexity, and thus, high production unit cost and a long production time are needed.
The channel length of the channel region C2 of the EDMOS transistor can be varied. If the channel length of the EDMOS transistor is formed to have the channel length of the LDMOS transistor, the EDMOS transistor may be used as the switching device. When the location of the interface between the P-type second well 22 and the N-type second well 23 is adjusted in order to decrease the channel length of the EDMOS transistor, space between the N-type source region 16 and the N-type second well 23 is decreased. Thus, breakdown voltage characteristic of the EDMOS transistor is seriously deteriorated.